Research activities
Since 2004. Politecnico di Milano. Researcher.
Since January, 5th he has become Researcher at the Electronics and
Information Technology Department of Politecnico di Milano. He works
in the field of digital and hardware/software design, embedded systems
design and methdologies, low-power design and real-time operating systems.
Since 1998. CEFRIEL. Research Consultant.
After his Master degree, he remains at CEFRIEL as a research consultant,
participating as technical manger in several IST Projecta.
He is also scientific tutor of the master students.
2001-2003. Politecnico di Milano. Consultant researcher.
Electronics and Information Technology department. He is participating to
teaching activities, programming laboratories, software development for
labs automation and other short-term research projects.
1995-1997. Italtel Central Research Labs. CAD Engineer.
He was in charge of maintaining the Italtel customized design flow for
FPGA devices and evaluating the new back-end tools. Part of his work
was devoted to support designers in the back-end phase of the design cycle.
To disseminate the know-how on FPGA technologies and design methodologies
he held a number of seminars to the designers of the Central Research
department in Castelletto and to the design teams of Italtel Difesa in L'Aquila.
Research interests
2007 - today. Wireless Sensor Networks
An important class of collaborating objects is represented by the myriad of wireless
sensors, which will constitute the infrastructure for the ambient intelligence vision.
The academic world actively investigates the technology for Wireless Sensor Networks (WSN).
Industry is reluctant to use these results coming from academic research. A major cause
is the magnitude of the mismatch between research at the application level and the node
and network level. The WASP project aims at narrowing this mismatch by covering the
whole range from basic hardware, sensors, processor, communication, over the packaging
of the nodes, the organisation of the nodes, towards the information distribution and
a selection of applications. The emphasis in the project lays in the self-organisation
and the services, which link the application to the sensor network.
Within this wide framework, particular attention has been devoted in defining,
designing and deployng a portable infrastructure capable of managing non-functional
aspects such as execution time, power consumption, quality of service, and so on.
The infrastructure plugs over an abstraction layer called WOS (WASP Operating
System) and is fully portable across diferent operaing systems. In order to minimize
the impact of the infrastructure a configuration mechanism is provided for automatically
generating the non-functional API in a very optimized way.
2003 - today. Embedded Systems Codesign
The Delta project has the goal of developing a co-design framework supporting
the design of heterogeneous embedded systems. The complexity of the
co-design approach enforces the composition of different and complementary
tasks: identification of metrics and estimators, development of models,
definition of methodologies, integration and tools implementation.
Such tasks are represented in the figure as concentric sectors on each
plane. The evolution of such tasks over time will lead to an improvement
of models and methodologies, as well as the introduction of new features,
better tool-chain integration oriented to the deployment of a pre-commercial
prototype tools. To face the complexity and variety of available target
platforms, the project will start from a well-defined architecture based
on the Xilinx Virtex-II Pro FPGA integrating a PowerPC processor core.
Such architecture allows studying the problems of platform configuration,
concurrent design of hardware and software portions, communication and
verification and is supported by the availability of a commercial development
kit - the Xilinx EDK. The evolution of the project will gradually consider
more and more complex, flexible and general platform-based architectures,
supported by a set of well-established commercially available EDA tools.
2001 - today. Power Optimization of Embedded Software
Based on the encouraging results obtained for software power estimation, the
optimization problem is currently being addressed, both from a theoretical
point of view and from a more practical standpoint. A complete comparative
analysis of all known source-to-source and assembly-level transformations
has been carried out using a free ISS. Original transformations have also
been envisaged and studied. A more accurate and comprehensive analysis will
be performed in the period 2001-2004 within the IST-2000-30125 Project POET.
2000. Performance and Power Analysis of Hetherogeneous Embedded Systems
Power estimation and optimization of software programs in standard
development environments. The results obtained during the Ph.D. and summarized
in the thesis are currently being extended in order to cover the C language
(instead of OCCAM2) and standard compilers (Sun cc, GNU gcc/egcs). The work
has the main purpose of modeling the power consumption of real-life industrial
applications taking into account all the aspects of a typical software design
flow, such as coding style, compiler, libraries and operating system.
The preliminary results are encouraging and suggest that source-level power
optimization might be considered.
1999. Neural Image Processing
Application of the neural approach to image processing. The problems studied
concerns the processing of digital images taken from CCD photographs of the
profile of the tracks of the Milan underground and of the result of keyhole
laser welding on automotive components. An overview on the problems of laser
welding, image processing and neuro-fuzzy control has been summarized in
an internal report. European Esprit Project TRACKS.
1999. Control Code Generation From Petri Nets Models
Analysis of the problem of automatic control code generation in the embedded
system environment based on a formal specification of the system behavior.
The system model is built using Functional Block Diagrams (FBD) and High
Level Timed Petri Nets (HLTPN). The work proposes a new methodology exploiting
a pattern-based decomposition of the Petri Net describing the system.
The decomposition is possible thanks to the structure of the Net enforced
by the higher-level FBD model. European Esprit Project INFORMA.
1997 - 2000. Hardware/Software Codesign From OCCAM-Based Specifications
The research work carried out during the Ph.D. is focused on the development
of methodologies and tools for concurrent hardware/software embedded systems,
and in particular to the power dissipation issues. The problems considered
concern the compilation of the parallel OCCAM language on a generic sequential
machine, the communication between the hardware and software partitions of a
design, the analysis and realization of a set of tools and libraries for the
translation of a Virtual Instruction Set code into an executable code for a
generic target processor. A significant part of the work focuses on the
problem of area, timing and power dissipation measurement of software programs
and has led to the development of three methodologies, and the corresponding
underlying models, for timing and power estimation of software at different
levels of abstraction (source level, intermediate level and assembly level).
The results of the work are collected in the prototype co-design environment
TOSCA. European Esprit projects SEED and PEOPLE.
1997. C++ Library For OCCAM-Based System-Level Specifications
Development of an object-oriented library (in C++) for representing thesyntactical
structure of the OCCAM language. The project required developing a syntax analyzer
and a grammar parser for the OCCAM language. The lexical analyzer and the parser
have been developed using the free software provided by GNU.
1995. Florplanning And Layout Methodology For Analog Integrated Circuits
Floorplanning and layout of analog integrated circuits. The work considers all
the aspects that influence the performances of an analog integrate circuit and
derives a quantitative model capable of assigning suitable weights to the
geometrical and topological constraints that usually need to be met when
performing IC floor-planning, placement and routing.
1992. Signed-Digit Arithmetic For Neural Network Processing
Analysis of different neural paradigms and realization of a digital cell
performing the function of a Pseudo-Neuron. The cell was developed using
academic tools such as 'espresso' and 'sis'.