Publications - Conferences

• C. Brandolese, N. Mainardi, M. Zanella, F. Reghenzani, N. Raspa,
  An Unsupervised Approach for Automotive Driver Identification,
  ACM Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications (INTESA'18),
  Torino, Italy, October, 2018.
• C. Brandolese, J. Flich et al.
  MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems,
  Euromicro Conference on Digital System Design (DSD'17),
  Vienna, Austria, August, 2017.
• C. Brandolese, S. Schreiner, et al.
  A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms,
  Euromicro Conference on Digital System Design (DSD'17),
  Vienna, Austria, August, 2017.
• C. Brandolese, A. Agneessens et al.
  Safe cooperative CPS: A V2I traffic management scenario in the SafeCOP project,
  International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS'16),
  Agios Konstantinos, Greece, July, 2016.
• C. Brandolese, M. K. Ariel Oleksiak et al.
  Data centres for IoT applications: The M2DC approach, (Invited paper)
  International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS'16),
  Agios Konstantinos, Greece, July, 2016.
• C. Brandolese, G. Agosta et al.
  V2I Cooperation for Traffic Management with SafeCop,
  Euromicro Conference on Digital System Design (DSD'16),
  Limassol, Cyprus, August, 2016.
• C. Brandolese, M. Cecowski et al.
  The M2DC Project: Modular Microserver DataCentre,
  Euromicro Conference on Digital System Design (DSD'16),
  Limassol, Cyprus, August, 2016.
• C. Brandolese, R. Goergen et al.
  CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties,
  Euromicro Conference on Digital System Design (DSD'16),
  Limassol, Cyprus, August, 2016.
• C. Brandolese, J. Flich et al.
  Enabling HPC for QoS-sensitive applications: The MANGO approach,
  Design, Automation and Test in Europe Conference and Exhibition (DATE'16),
  Dresden, Germany, March, 2016.
• C. Brandolese, M. Grotto et al.
  Playful Supervised Smart Spaces (P3S) -- A Framework for Designing, Implementing and Deploying Multisensory Play Experiences for Children with Special Needs,
  Euromicro Conference on Digital System Design (DSD'15),
  Funchal, Madeira, Portugal, August, 2015.
• C. Brandolese, L. Rucco, W. Fornaciari
  An optimal model to partition the evolution of periodic tasks in wireless sensor networks,
  IEEE International Symposium on a World of Wireless, Mobile and Multimedia Networks (WoWMoM'14),
  Sydney, Australia, July, 2014.
• C. Brandolese, L. Rucco, W. Fornaciari
  Optimal wakeups clustering for highly-efficient operation of WSNs periodic applications,
  International Conference on Information Communication and Embedded Systems (ICICES'14),
  Chennai, Tamil Nadu, India, February, 2014.
• C. Brandolese, W. Fornaciari, L. Rucco
  A Formal Model for Optimal Autonomous Task Hibernation in Constrained Embedded Systems,
  EUROMICRO Conference on Digital System Design, (DSD'13),
  Santander, Spain, September 2013.
• C. Brandolese, W. Fornaciari, L. Rucco
  Power Management Support to Optimal Duty-Cycling in Stateful Multitasking WSN,
  IEEE International Symposium on Parallel and Distributed Processing with Applications (TrustCom-13),
  Melbourne, Australia, July, 2013.
• C. Brandolese, W. Fornaciari, L. Rucco
  Optimal Hibernation Policies for Energy Efficient Stateful Operation in High-end Wireless Sensor Nodes,
  IEEE International Symposium on a World of Wireless, Mobile and Multimedia Networks (WoWMoM'13)
  Madrid, Spain, June 2013.
• L. Rucco, A. Bonarini, C. Brandolese, W. Fornaciari
  A Bird's Eye View on Reinforcement Learning Approaches for Power Management in WSNs,
  IEEE/IFIP Wireless and Mobile Networking Conference (WMNC'13)
  Dubai, United Arab Emirates, April 2013.
• C. Brandolese, W. Fornaciari, L. Rucco, F. Terraneo
  Introducing Smart Drivers - A Way to Conceive Smart Data Sensing in Wireless Sensor Networks,
  IEEE International Conference on Information Communication and Embedded Systems (ICICES'13)
  Chennai, Tamilnadu, India, February 2013.
• C. Brandolese, W. Fornaciari
  Software Energy Optimization Through Fine-Grained Function-Level Voltage and Frequency Scaling,
  IEEE/SIGDA International Conference on Hardware/Software Codesign and System Synthesis, (CODES+ISSS')
  Tampere, Finland, October 2012.
• C. Brandolese, W. Fornaciari, L. Rucco, F. Terraneo
  Enabling Ultra-Low Power Operation in High-End Wireless Sensor Networks Nodes,
  IEEE/SIGDA International Conference on Hardware/Software Codesign and System Synthesis, (CODES+ISSS'12)
  Tampere, Finland, October 2012.
• C. Brandolese, W. Fornaciari, G. Palermo et. al.,
  COMPLEX - COdesign and power Management in PLatform-based design space EXploration,
  The 15th EUROMICRO Conference on Digital System Design, (DSD'12)
  Cesme, Izmir, Turkey, September 2012.
• C. Brandolese, W. Fornaciari, L. Rucco, D. Zoni
  Towards Energy-Efficient Functional Configuration in WSNs,
  IFAC/IEEE International Conference on Programmable Devices and Embedded Systems, (PDES'12)
  Brno, Chzech Republic, May 2012.
• C. Brandolese, W. Fornaciari, L. Rucco, D. Zoni
  Power-efficient software allocation in Wireless Sensor Networks, (poster)
  IEEE Conference on Design Automation and Testing in Europe, (DATE'12)
  Dresden, Germany, March 2012.
• S. Bocchio, C. Brandolese, S. Corbetta, W. Fornaciari,
  A Methodology and a Case Study of Dynamic Power Management for Embedded Systems, (Invited paper)
  Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes, (FETCH'12)
  Alpe d'Huez, France, January 2012.
• C. Brandolese, S. Corbetta, W. Fornaciari
  Software Energy Estimation Based on Statistical Characterization of Intermediate Compilation Code,
  International Symposium on Low Power Electronics and Design, (ISLPED'11)
  Fukuoka, Japan, August 2011.
• C. Brandolese, L. Rucco,
  Optimization of Functional Allocation to Maximize the Lifetime of Wireless Sensor Networks,
  IEEE Conference on Wireless Communication and Sensor Networks, (WCSN'10)
  Allahabd, India, December 2010.
• C. Brandolese, L. Rucco,
  A Genetic Approach for WSN Lifetime Maximization Through Dynamic Linking and Management,
  ACM International Symposium on Performance Evaluation of Wireless Ad Hoc, Sensor, and Ubiquitous Networks, (PE-WASUN'10)
  Bodrum, Turkey, October 2010.
• C. Brandolese, W. Fornaciari, D. P. Scarpazza,
  Source-Level Energy Estimation and Optimization of Embedded Software,
  IEEE Latin America Symposium on Circuits and Systems, (LASCAS'10)
  Foz do Iguazu, Paranà, Brazil, February 2010.
• C. Brandolese, W. Fornaciari, L. Rucco,
  A Lightweight Mechanism for Dynamic Linking in Wireless Sensor Networks,
  IEEE Latin America Symposium on Circuits and Systems, (LASCAS'10)
  Foz do Iguazu, Paranà, Brazil, February 2010.
• C. Brandolese, W. Fornaciari,
  A framework for compile-time and run-time management of non-functional aspects in WSNs nodes,
  The 12th EUROMICRO Conference on Digital System Design, (DSD'09)
  Patras, Greece, September 2009.
• C. Brandolese, W. Fornaciari,
  Measurement, Analysis and Modeling of RTOS System Calls Timing,
  The 11th EUROMICRO Conference on Digital System Design, (DSD'08)
  Parma, Italy, September 2008.
• C. Brandoese,
  Source-Level Estimation of Energy Consumption and Execution Time of Embedded Software,
  The 11th EUROMICRO Conference on Digital System Design, (DSD'08)
  Parma, Italy, September 2008.
• C. Brandolese D. Crespi, L. Frigerio, F. Salice,
  A New Framework for Design and Simulation of Complex Hardware/Software Systems,
  The 10th EUROMICRO Conference on Digital System Design, (DSD'07)
  Lubeck, Germany, August 2007.
• C. Brandolese, C. Bolchini, L. Frigerio, V. Rana, F. Salice, M. Santambrogio,
  RoadRunner and IPGen: A Combined Solution to Speedup Configurable Systems Design,
  The 3rd Southern Conference on Programmable Logic, (SPL'07)
  Mar del Plata, Argentina, February 2007.
• C. Brandolese, W. Fornaciari, L. Pomante, F. Salice, R. Zafalon,
  DPM at OS level: low-power scheduling policies,
  WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processes, (CSECS'06), pp. 100-105
  Dallas, TX, USA, November 2006.
• C. Brandolese, C. Bolchini, W. Fornaciari, L. Frigerio, F. Salice,
  A Data- Path Oriented, IP-Based Framework for Flexible Design Exploration,
  IEEE Electronic Design Processes Workshop, (EDP'06),
  Monterey, CA, USA, April 2006.
• C. Brandolese, P. Di Felice, L. Pomante, D.P. Scarpazza,
  Parsing SystemC: An Open-Source, Easy-to-Extend Parser,
  International Conference on Applied Computing, (IADIS'06),
  San Sebastian, Spain, February 2006.
• C. Brandolese, W. Fornaciari, F .Salice,
  A SoC-Based Methodology for Cycle-Accurate RTOS System Call Timing Characterization,
  IEEE Conference on Design of Circuits and Integrated Systems, (DCIS'05)
  Lisbon, Portugal, November 2005.
• C. Brandolese, W. Fornaciari, F. Salice,
  Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures,
  Power and Timing Modeling, Optimization and Simulation, (PATMOS'04), pp. 238-247,
  Santorini, Greece, September 2004.
• C. Brandolese, W. Fornaciari, F. Salice,
  An Area Estimation Methodology for FPGA Based Designs at SystemC-Level,
  IEEE Design Automation Conference, (DAC'04), pp. 129-132,
  San Diego, CA, USA, June 2004.
• C. Brandolese, F. Curto, W. Fornaciari, F. Salice,
  Analysis and Modeling of Energy Reducing Source Code Transformations,
  IEEE Conference on Design Automation and Testing in Europe, (DATE'04), pp. 306-311,
  Paris, France, February 2004.
• C. Brandolese, W. Fornaciari, F. Salice e D. Sciuto,
  Library Functions Timing Characterization for Source-Level Analysis,
  IEEE Conference on Design Automation and Testing in Europe, (DATE'03), pp. 1132-1133,
  Munich, Germany, March 2003
• C. Brandolese, W. Fornaciari,
  Power-Aware Design of Embedded Software,
  Windriver User's Group Forum, (WindForum'02),
  Baveno, Italy, November 2002.
• C. Brandolese, G. Beltrame, W. Fornaciari, F. Salice, D. Sciuto e V. Trianni,
  Modeling Assembly Instruction Timing in Superscalar Architectures,
  IEEE International Symposium on System Synthesis, (ISSS'02), pp.132-137,
  Kyoto, Japan, October 2002.
• C. Brandolese, G. Beltrame, W. Fornaciari, F. Salice, D. Sciuto, V. Trianni,
  An Assembly-Level Execution-Time Model for Pipelined Architectures,
  IEEE/ACM International Conference on Computer Aided Design, (ICCAD'01), pp. 195-200,
  San Jose, CA, USA, November 2001.
• C. Brandolese, G. Beltrame, W. Fornaciari, F. Salice, D. Sciuto, V. Trianni,
  Dynamic Modeling of Inter-Instruction Effects for Execution Time Estimation,
  IEEE International Symposium on System Synthesis, (ISSS'01), pp. 136-141,
  Montreal, Canada, October 2001.
• C. Brandolese, W. Fornaciari, F. Salice e D. Sciuto,
  Source-Level Execution Time Estimation of C Programs,
  IEEE International Workshop on Hardware Software Co-design, (CODES'01), pp. 98-103,
  Copenhagen, Denmark, April 2001.
• C. Brandolese, W. Fornaciari, L. Pomante, F. Salice e D. Sciuto,
  A Multi-Level Strategy for Software Power Estimation,
  IEEE International Symposium on System Synthesis, (ISSS'00), pp. 187-192,
  Madrid, Spain, September 2000.
• C. Brandolese,
  Retargetable Software Power Estimation Methodology,
  IFIP Asia Pacific Conference on Hardware Description Languages, (WCC-ICDA'00), pp. 408-412,
  Beijing, China, August 2000.
• C. Brandolese, W. Fornaciari, F. Salice e D. Sciuto,
  An instruction-level functionality-based energy estimation model for 32-bits microprocessors,
  IEEE Design Automation Conference, (DAC'00), pp. 346-351,
  Los Angeles, CA, USA, June 2000.
• C. Brandolese, W. Fornaciari, F. Salice e D. Sciuto,
  Energy estimation for 32-bit microprocessors,
  IEEE International Workshop on Hardware Software Co-design, (CODES'00), pp. 24-28,
  San Diego (CA), May 2000.
• C. Brandolese, W. Fornaciari, F. Salice e D. Sciuto,
  Fast Software-Level Power Estimation for Design Space Exploration,
  International Conference on Hardware Description Languages, (HDLCon'00), pp. 11-16,
  San Jose, CA, USA, March 2000.
• C. Brandolese, A. Allara, W. Fornaciari, F. Salice e D. Sciuto,
  System-Level Performance Estimation Strategy for SW and HW,
  IEEE International Conference on Computed Design, (ICCD'98), pp. 48-53,
  Austin, Texas, USA, October 1998.
• C. Brandolese, M. Pillan, F. Salice e D. Sciuto,
  Analog Circuit Placement: A Constraint Driven Methodology,
  IEEE International Symposium on Circuit and System, (ISCAS'96), pp. 635-638,
  Atlanta, Georgia, USA, May 1996.
• C. Brandolese, M. Pillan, F. Salice e D. Sciuto,
  A Deterministic, Constraint-Driven Placement Methodology for Ananlog Circuits,
  IEEE International Conference on Microelectronics, (ICM'95),
  Kuala Lumpur, Malaysia, December 1995.